1. Field of Invention
The present invention relates to a circuit structure for connecting a bonding pad and an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates a multiple path circuit structure for connecting a bonding pad and an ESD protection circuit such that the multiple paths permit the discharge of a larger current and hence improve circuit protection capacity.
2. Description of Related Art
Electrostatic discharge is a phenomenon that occurs when static charge moves on a non-conducting surface. Sudden movement of electric charges inside the semiconductor material of an integrated circuit (IC) package often leads to circuit failure. For example, somebody walking across a carpet may pick up static charges. If the surrounding air has a high relative humidity (RH), the body of a person may charge up to a few thousand volts. However, if the surrounding air has a low RH, the body of a person may charge up to ten thousand or more volts. IC packaging machines or testing equipment may also accumulate charges and produce from several hundred to several thousand volts of static electricity. As the aforementioned charged bodies (human, machine or equipment) come in contact with a silicon chip, the sudden surge in power due to the sudden movement of static charges through the chip may damage the internal circuits or cause malfunction.
To minimize the damaging effect of electrostatic discharge on integrated circuits, special ESD protection schemes have been developed. The most common method is the provision of a hardware discharge route. In other words, an on-chip ESD protection circuit is provided between the internal circuit and each bonding pad.
FIG. 1 is a schematic cross-sectional view showing a conventional circuit structure that connects an ESD protection circuit with the bonding pad of a semiconductor device. FIG. 2 is a perspective view of the circuit structure shown in FIG. 1. Note that the dielectric layers in FIGS. 1 and 2 are not shown. As shown in FIGS. 1 and 2, the bonding pad 100 is formed in the uppermost layer of the semiconductor device and the ESD protection circuit 118 is formed within the substrate 50. The bonding pad 100 connects sequentially, in a downward direction, with a via 102, a conductive layer 104, a second via 106, a second conductive layer 108, a third via 110, a third conductive layer 112. The third conductive layer 112 has an extension line 112a that extends to a region above the drain terminal 116 of the ESD protection circuit 118. The extension line 112a and the drain terminal 116 are connected through a contact 114. In addition, an insulating layer 130 encloses the aforementioned circuit components and separates the bonding pad 100 from the substrate 50.
During an electrostatic discharge, static electricity flows from the bonding pad 100 to the ESD protection circuit 118 via an external circuit. In other words, current discharges from the bonding pad 100 via the first via 102, the first conductive layer 104, the second via 106, the second conductive layer 108, the third via 110, the third conductive layer 112, the extension line 112a and the drain terminal 116 of the ESD protection circuit 118. Since static charges are channeled away via the ESD protection circuit 118, possible damage to the internal circuits is prevented.
According to FIGS. 1 and 2, static electricity is discharged through the single metallic layer (that is, the extension line 112a) to the ESD protection circuit 118. When a sufficiently large current flows through the extension line 112a, the extension line 112a may fuse leading to malfunction of the ESD protection circuit 118. To prevent the fusing of the extension line 112a due to an over-current, width of the extension line 112a is increased. However, as semiconductor devices continue to be miniaturized, a widening of line width implies a lowering of processing window as well as level of integration.